The present invention relates generally to adders and more specifically to an adder to be used with multipliers and digital signal processors.
A full adder is an adder which adds the two numbers together and includes for each bit a sum and a carry output in response to a pair of binary bit inputs and a carry input from the previous stage. Static adders, or those that are not precharged, have logic to bias the output high as well as biasing it low for appropriate input signals. Prior art adders generally include a carry gate and a sum gate each being connected to the two-bit input and the carry input. A typical carry gate G1 of the prior art is illustrated in FIG. 1 as including N channel devices N1 through N5 connected between ground and the output C.sub.N and P channel devices P1 through P5 connected between V+ and the output C.sub.N. The gates are connected respectively to the bit inputs A.sub.N and B.sub.N as well as the carry from the previous stage, C.sub.N-1. The output: EQU C.sub.N =A.sub.N B.sub.N +C.sub.N-1 (A.sub.N +B.sub.N)
In this gate, each of the bit inputs A.sub.N and B.sub.N are connected to a minimum of four transistors and the carry from the previous stage C.sub.N-1 is connected to a pair of transistors.
The sum gate G2 is illustrated in FIG. 2 as including N channel transistors N11 through N17 and P channel transistors P11 through P17 connected between ground and V+ respectively and the output S.sub.N. Again, each of the bit inputs A.sub.N and B.sub.N are connected to four transistors, the carry from the previous stage C.sub.N-1 is connected to four transistors, and the carry signal from the present stage C.sub.N is connected to a pair of transistors. The sum gate G2 has a maximum stack of three transistors high between a voltage source and the output terminal. Thus, between the two gates G1 and G2 there are 24 transistors, having a minimum stack height of two and a maximum stack height of three, and the inputs A.sub.N and B.sub.N are connected respectively to eight transistors, and the input C.sub.N-1 is connected to six transistors. This is a substantial fan out of the input signal.
Thus, it is an object of the present invention to provide an improved full adder including improved carry gates and sum gate.
Another object of the present invention is to provide an improved full adder which minimizes fan-out of the input signal.
An even further object of the present invention is to provide an adder with reduced transistor stack height.
A still even further object of the present invention is to provide a carry gate of reduced input signal fan-out and stack height.
An even further object of the present invention is to provide a sum gate having reduced input signal fan-out and stack height.
These and other objects are obtained by providing first and second input gates and an input inverter for preprocessing the input signals, a carry gate and a sum gate. The first input gate is connected to each of the input bits for providing a logic low output only when all its inputs are a logic high. The second input gate is connected to each of the input bits for providing a logic high only when all of its inputs are a logic low. The inverter provides the inverse of an additional input bit if the inverse is not available. The carry gate has three inputs and provides a carry-out logic high output when either (a) its first input from the first logic gate is a logic low; or (b) when both the second input from the second input gate and the third input from the inverter are a logic low. The sum gate has five inputs and provides a sum logic high output when either (a) both its first and second inputs from the output of a first input gate and from the inverter are logic low; or (b) its third input from the carry gate is at a logic low and either of the fourth or fifth inputs from the inverter or the second input gate are respectively a logic low.
The carry gate includes a first switch connected between the carry gate output and a logic source which is activated by a low signal from the first input gate. A pair of series connected second and third switches connects the logic high supply and the carry gate output and is activated respectively by a low from the output of the second input gate and the output of the inverter. A fourth switch connects a logic low supply to the carry gate output and is activated by a logic high at the output of the second input gate. A pair of series connected fifth and sixth switches connect the logic low supply and the carry output and are activated respectively by high signals on the output of the first input gate and the output of the inverter.
The sum gate includes first and second switches connected in series between a logic high supply and the sum gate output and activated respectively by lows on the output of the first input gate and the inverter. A third switch is connected in series with the parallel connection of a fourth and fifth switch between the logic high supply and the sum gate output and activated respectively by logic lows on the output of the carry gate and either the second input gate or the inverter. The sum gate also includes a sixth and seventh switch connected in series between the logic low supply and the sum gate output and activated by high signals on the output of the second input gate and the inverter. An eighth switch is connected in series with a parallel connection of a ninth and tenth switch between the logic low supply and the sum gate output and activated respectively by logic highs on the output of the carry gate and either the first input gate or the inverter.
The first and second input gates for two bits each include a first and second transistor connected between a first logic supply and the output in parallel and third and fourth transistors connected between a second logic supply and the output in series. The inputs are each connected to one of the parallel switches and one of the series switches.
The first and second input logic gates each include four transistors having a minimum stack of one and a maximum stack of two and the inverter includes a pair of transistors having a maximum stack of one. The input signals of each bit are connected only to four transistors with the input signal of the carry-in from the previous stage being connected to only two transistors. The carry gate includes six transistors having a minimum stack height of one and a maximum stack height of two and each of its inputs are connected only to a pair of transistors. The sum gate includes ten transistors having a minimum and maximum stack height of two with each of its inputs connected to two transistors. Although the input signals have a maximum fan-out of four, the maximum internal fan-out of any signal is the output of the inverter or the carry-in signal from the previous stage which has a fan-out of six.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.